Singapore markets open in 3 hours 52 minutes

Synopsys, Inc. (SYNP.VI)

Vienna - Vienna Delayed price. Currency in EUR
Add to watchlist
558.70-0.60 (-0.11%)
At close: 05:32PM CEST
Full screen
Previous close559.30
Open558.40
Bid555.70 x N/A
Ask561.80 x N/A
Day's range558.40 - 558.70
52-week range388.00 - 581.50
Volume0
Avg. volume0
Market cap85.602B
Beta (5Y monthly)1.07
PE ratio (TTM)65.27
EPS (TTM)N/A
Earnings dateN/A
Forward dividend & yieldN/A (N/A)
Ex-dividend dateN/A
1y target estN/A
  • PR Newswire

    Synopsys Accelerates Chip Innovation with Production-Ready Multi-Die Reference Flow for Intel Foundry

    Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of its production-ready multi-die reference flow, powered by Synopsys.ai™ EDA suite, and Synopsys IP for Intel Foundry's embedded multi-die interconnect bridge (EMIB) advanced packaging technology. The optimized reference flow provides a unified co-design and analysis solution, enabled by Synopsys 3DIC Compiler to accelerate exploration and development of multi-die designs at all stages from silicon to systems. In addition, Synopsys

  • PR Newswire

    Synopsys Achieves Certification of its AI-driven Digital and Analog Flows and IP on Samsung Advanced SF2 GAA Process

    Synopsys, Inc. (Nasdaq: SNPS) today announced that its AI-driven digital design and analog design flows have achieved certification on Samsung Foundry's SF2 process with multiple test chip tapeouts. The reference flows, powered by the Synopsys.ai™ full-stack EDA suite, enhance PPA, boost productivity, and accelerate analog design migration for Samsung Foundry's latest Gate-All-Around (GAA) process technologies. The Samsung SF2 process was optimized using Synopsys' AI-driven design technology co-

  • PR Newswire

    Synopsys Accelerates Trillion Parameter HPC & AI Supercomputing Chip Designs with Industry's First PCIe 7.0 IP Solution

    Synopsys, Inc. (Nasdaq: SNPS) today announced the industry's first complete PCIe 7.0 IP solution consisting of controller, IDE security module, PHY, and verification IP. This solution will enable chip makers to address the demanding bandwidth and latency requirements of transferring massive amounts of data for compute-intensive AI workloads while supporting broad ecosystem interoperability. Large language models' demand for computational capabilities is growing at a breakneck pace, with trillion